Memory-efficient architecture for FrWF-based DWT of high-resolution images for IoMT applications

This paper proposes a simple low memory architecture for computing discrete wavelet transform (DWT) of high-resolution (HR) images on low-cost memory-constrained sensor nodes used in visual networks (VSN) or Internet Multimedia Things (IoMT). The main feature the proposed is novel data scanning technique that makes requirement independent image size. needs only (30S) words memory, where S number parallel processing units and critical path delay (CPD) equal to multiplier (Tm). Furthermore, multiplierless version this also which reduces CPD Ta<Tm (where Ta an adder). In order evaluate their effectiveness, architectures are coded HDL implemented same FPGA board. Their performance compared with other state-of-the-art DWT architectures. experimental results show superiority terms existing Moreover, reduction indicates operating frequency can be scaled up by several factors chosen depending upon application. Compared one best architecture, (with = 4) 57.37% less LUT’s 64.39% flip-flops HR dimension 2048 × 2048. no LUTRAM DSP, whereas requires 3264 24 DSP’s. Thus superior suitable IoMT/VSNs.